WEBVTT

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The signature fails and the register stores zero.

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A pulse briefly inverts the observed value at
edge three, then ends before the request at edge

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four.

4
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No unauthorized fetch occurs, although no
detector was present.

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Fix the baseline: reset at edge zero,
verification at edge two, ready requests at edges

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four and six, and observation through edge seven.

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Both requests share one fault budget for the same
boot attempt.

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Checked records completion, while result stores
pass or fail.

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Grant ANDs checked with the observed result.

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Count accepted commit at a rising edge only when
fetch valid, receiver ready, and grant all hold.

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This is a simplified fetch handoff, not execution
or instruction retirement.

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A changed upstream value matters when it reaches
this acceptance edge.

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Separate two paths.

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A inverts the Q seen by downstream logic,
returning to normal when the control ends; the

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stored value does not change.

16
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B modifies storage, so later reads remain wrong
after its control ends.

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The name bit flip fits both, but what makes the
error disappear is different.

18
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Location, duration, and sampling time determine
what a request actually sees.

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A model card begins with the event to protect: an
unauthorized image must obtain no accepted fetch.

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Add initialization, requests, and deadline.

21
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For B, target the stored result, invert once, and
retain it until normal overwrite or reset.

22
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This is not a continually forced one.

23
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The state-transition experiment should be
reproducible from the card.

24
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Moving the target to clock or checker requires a
different card.

25
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At each edge, first sample old Q and grant and
record acceptance.

26
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Then update the registers normally.

27
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Finally apply B's inversion to the new state.

28
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An upset after edge three affects what edge four
reads; it cannot revise the event already

29
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recorded at edge three.

30
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Keep those phases separate instead of explaining
pre-update acceptance with post-update Q.

31
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An event count, location count, and bit count
impose different limits.

32
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One upset at edge three can affect requests at
four and six while remaining one event.

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Inversions at three and five are two events, even
on the same bit.

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The budget covers reset through edge seven and
restarts with another reset.

35
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Device-lifetime retry limits are a separate
product assumption; a per-attempt bound does not

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provide permanent assurance.

37
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Trust the image, policy, and independent
reference.

38
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Also exclude clock, reset, completion, checked,
nontarget logic, and the acceptance mechanism

39
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from disturbance.

40
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The reference retains the original failure rather
than copying the attacked result.

41
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These exclusions isolate a small question.

42
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They do not establish physical immunity or
inaccessibility for those components in a

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product.

44
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Case A adds a test XOR on the read path.

45
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Its control inverts the observed value, then
restoring zero reveals original Q again.

46
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Without feedback to D, storage stays unchanged.

47
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A pulse ending after edge three misses the
request at four, which reads zero.

48
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Move that pulse onto a request edge and the
outcome can change.

49
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The original run missed sampling; it did not
exercise an active defense.

50
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Case B selects the normal next state and applies
one XOR before storage.

51
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After edge three, failure zero becomes one.

52
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The injector returns to zero, but the hold path
retains that one, so requests at four and six are

53
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accepted.

54
00:04:08.374 --> 00:04:11.916
One injection caused both accepted requests.

55
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This RTL-style construction specifies a storage
effect; it does not establish physical coupling

56
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of a laser or electromagnetic disturbance to D.

57
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Case C inverts auth okay before storage.

58
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Cover the completion write at edge two and the
wrong answer is captured, surviving the pulse.

59
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A pulse at edge three misses that write: checked
has already closed the enable, so result stays

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unchanged.

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Inspect verify done, checked, and the actual
write condition together.

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C and B use separate traces, without simultaneous
source and storage injection.

63
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In an RTL testbench, stabilize controls before
sampling and distinguish pre-update from

64
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post-update observations.

65
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Changing injection controls with blocking
assignments at the same positive edge can let DUT

66
00:05:03.961 --> 00:05:06.031
and monitor see different ordering.

67
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The Python model does not simulate event-region
races, within-cycle glitches, or metastability.

68
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A simulator harness must address those behaviors
separately.

69
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Force, release, backdoor deposit, and injection
multiplexers name methods, with effects depending

70
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on the simulator, net or variable, and normal
updates.

71
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The fi signals reproduce specified faults; they
provide no protection and should be removed from

72
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production.

73
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Record the target, effect, and recovery.

74
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An API name alone cannot let another engineer
reproduce the same behavior.

75
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In a separate D trace, invert final grant from
zero to one at edge four.

76
00:05:47.798 --> 00:05:53.745
Upstream still correctly records failure, but the
receiver can now accept.

77
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A, B, and C excluded this location, so their
results do not cover it.

78
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D still trusts the handshake and actual
acceptance mechanism, without evaluating every

79
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consumer node.

80
00:06:06.738 --> 00:06:10.362
Adding a target changes the trusted boundary.

81
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Every accepted commit must agree with independent
reference completion and authorization at that

82
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same sampling edge.

83
00:06:18.625 --> 00:06:22.159
A later alert cannot substitute for this
requirement.

84
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Exclude reset and enforce the fault budget in the
harness.

85
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The supplied assertion example can be
incorporated into further verification, but this

86
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animation does not claim a compiled assertion or
completed formal proof.

87
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With an authorized image, fetch acceptance should
be reachable.

88
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A cover can find such a path without guaranteeing
progress on every valid boot.

89
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Specify progress, timeout, and recovery
separately.

90
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Permanently denying fetch might satisfy the
narrow safety property while preventing the

91
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device from working.

92
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Report safety and authorized operation as
distinct outcomes.

93
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Choose six starting edges, two through seven.

94
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A, C, and D test one- or two-edge pulses; B
applies one inversion per start.

95
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That gives forty two fault cases plus two
fault-free controls, each independently reset

96
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with the same failed image and requests.

97
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Python reports eighteen unauthorized traces and
twenty four without acceptance in the window.

98
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PASS reproduces expected behavior, including
deliberate bypasses.

99
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The ratio is not a physical success rate:
probability, disturbance strength, and

100
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reachability were not measured.

101
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If B acts after edge six, the final original
request has already sampled, leaving no later

102
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acceptance opportunity.

103
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Add a request at edge seven and the retained one
is used, permitting acceptance.

104
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The earlier run did not evaluate that
opportunity.

105
00:07:54.464 --> 00:08:00.879
Include the workload in a protection comparison,
or identical stored corruption can produce

106
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apparently conflicting outcomes.

107
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Save design and model versions, target, injection
settings, initialization, requests, deadline, and

108
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counterexample trace.

109
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Check whether injection took effect, whether a
sensitive request arrived, and whether the

110
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property ran.

111
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Keep missing requests, timeouts, failed
injections, and disabled assertions unresolved

112
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instead of counting them as safety passes.

113
00:08:24.844 --> 00:08:29.218
A reproducible campaign preserves these
distinctions in its records.

114
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Before comparing SYNFI, VerFI, or FIRMER, align
targets, effects, event budgets, timing, and

115
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observation points.

116
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Netlist analysis, SAT-based proof, and this
edge-by-edge program may use different

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assumptions.

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This lesson does not run those tools or reproduce
their benchmarks.

119
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Their numbers cannot be combined into one
protection guarantee without matching the

120
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underlying models.

121
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A product may expose prefetch, DMA, debug, or key
reads, each with a sensitive handoff.

122
00:08:59.826 --> 00:09:06.186
Match RTL targets to the netlist and calibrate
effects against physical tests, checking that

123
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blocking precedes acceptance.

124
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Clock and reset faults, multiple bits, repeated
injection, and information leakage need

125
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additional models.

126
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This single-attempt result over a finite window
does not cover them.

127
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Put the B upset after edge six on a model card.

128
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Run the original requests, then add edge seven.

129
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Specify the target, effect, budget, trusted
components, and deadline, reporting acceptance,

130
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detection, and timely blocking separately.

131
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A colleague can then distinguish a workload
change from protection taking effect.

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Use the same acceptance event and experimental
discipline when comparing storage codes.