Read RTL as the hardware floor plan
This guide is not asking you to write a perfect AES core on the first pass. Start by reading RTL as a floor plan: where data enters, where it waits, which block transforms it, and when the controller says the result is valid.
AES gives the algorithmic steps. RTL turns those steps into clocked hardware with registers, datapaths, round control, and timing rules.
When the signal names feel dense, ask three questions: where is the data now, where does it move next, and what control signal allows that move?
Start from the datapath before writing modules
AES-128 RTL becomes much easier when the state mapping, round structure, and valid/ready timing are defined first. Otherwise, byte order and control timing become recurring bugs.
A clean design separates the key schedule, round transformation, final round, and control FSM while keeping the state layout consistent with the AES specification.
Good RTL is also good documentation
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
Good RTL is also good documentation (3)
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
Good RTL is also good documentation (4)
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
Good RTL is also good documentation (5)
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
Good RTL is also good documentation (6)
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
Good RTL is also good documentation (7)
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
Good RTL is also good documentation (8)
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
Good RTL is also good documentation (9)
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
Good RTL is also good documentation (10)
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
Good RTL is also good documentation (11)
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
Good RTL is also good documentation (12)
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
Good RTL is also good documentation (13)
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
Good RTL is also good documentation (14)
Clear sub-block boundaries, explicit input/output definitions, and simple test vectors make the implementation easier to review and reuse. The goal is not just a working AES core, but a core that can be verified and maintained.
References
- NIST FIPS 197: Advanced Encryption Standard: The authoritative byte-level AES algorithm reference.
Learning guide
From AES to RTL
Prerequisites
- AES round operations and synchronous logic
What I learned
- Partition AES into datapath and control
- Define valid/ready behavior
- Keep byte ordering consistent