LEARNING PATHS
Choose a path, read each lesson, take the short quiz, and keep your progress in this browser—no account required.
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Understand hashes, encryption, identities and secure channels before choosing a mechanism.
For readers starting with security concepts.
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Follow trust from device identity and key storage through boot, attestation and updates.
For chip architects and system designers.
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Start with a firmware digest or an encrypted sensor block. Build the datapath and transfer rules, then test whether corrupted results can grant permission.
For readers with basic registers, bit operations and synchronous RTL. Begin with SHA-256 or AES, then follow Anti-Tampering Lessons 1–3 in order.
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Connect design claims to evaluation evidence, certification scope and product lifecycle duties.
For technical leads and product teams.
Explore this track →Follow performance from the core pipeline through caches, coherence, the NoC, and coherent expansion.
Explore the 26-lesson curriculum: single cores, parallel work, memory systems, Arm, RISC-V, and optional CPU design labs.
Follow data from the CPU and accelerator through memory bandwidth, HBM stacks, repair, and packaging.
A growing series on LLM inference, tokens, KV cache, memory movement, and AI accelerator architecture.