Error-correcting Code
Extra check bits help detect or correct specified errors. Their protection depends on the code, use policy and fault model.
GLOSSARY
Terms that connect the lessons.
Use each definition as a bridge back to the articles where the idea matters.
Fault Injection
Deliberately perturbing a circuit to test or exploit faulty behavior under a stated model.
Fault Model
The allowed targets, effects, timing, fault budget and trusted boundaries of an experiment.
Accepted Commit
The interface event at which the downstream consumer accepts a protected operation.
TLS
Establishes a transport channel with applicable authentication and data protection.
ECDHE
Agrees a shared secret using ephemeral elliptic-curve key material.
HKDF
Extracts and derives purpose-specific material; it does not manufacture entropy.
Transcript
The handshake-message history accumulated under the protocol's rules.
CertificateVerify
Binds the corresponding private-key capability to the current handshake using a signature.
Finished
Confirms the handshake and keys through a derived-key MAC.
AEAD
Combines encryption and authentication for record protection.
mTLS
Uses certificates to authenticate both TLS peers; authorization remains separate.
Forward secrecy
Under its assumptions, later long-term-key compromise does not reveal past session keys.
0-RTT
Early data sent before handshake completion, with different replay and secrecy guarantees.
Digital Signature
Evidence created with a private key and checked with a public key for a particular message; key identity and usage policy remain separate requirements.
Certificate
A signed data structure that binds a public key to an identity or other attributes under an issuer's policy.
PKI
The roles, policies, systems, and lifecycle processes used to issue, validate, renew, and revoke public-key certificates.
X.509
A standard framework for public-key certificates and certification paths.
Trust Anchor
A locally accepted starting point for trust decisions, such as a public key, key digest, or root certificate used by Secure Boot or certificate-path validation.
Secure Boot
A startup policy that authenticates covered next-stage code before granting it execution.
Threat Model
A structured description of assets, attacker capabilities, reachable entry points, assumptions, and potential impact used to choose defenses.
TEE
A hardware- and software-supported isolated environment for sensitive code or data; isolation depends on implementation and configuration and is not absolute security.
Anti-rollback
A protected version policy that rejects authenticated software older than the minimum version currently allowed.
Cache Coherence
The rules that keep cached copies of one address consistent across agents.
MESI
A cache-coherence protocol built around Modified, Exclusive, Shared, and Invalid states.
False Sharing
Unrelated writes contend because their variables occupy the same cache line.
SHA
A family of cryptographic hash algorithms that maps arbitrary-length data to a fixed-length digest.
PUF
A circuit that uses physical variation to produce device-dependent responses; reliability and secrecy require separate evaluation.
AES
A symmetric block cipher that transforms 128-bit blocks through repeated rounds.
RTL
A clock-aware hardware description of registers, data paths, and control transfers.
Throughput
Useful work completed per unit time under a stated workload and measurement method.
Amdahl's Law
A bound on speedup for a fixed workload when a serial fraction cannot be parallelized.
IPC
Instructions completed per clock cycle; a key measure beyond frequency.
MLP
Memory-level parallelism: overlapping multiple outstanding memory operations.
HBM
Stacked DRAM connected through a very wide, short interface for high bandwidth.
TSV
A vertical electrical connection passing through a silicon die.
ABF
A fine-line build-up film used as dielectric material in advanced package substrates.
CXL
A PCIe-based interconnect family for I/O, coherent device caching, and expandable memory.
ASIC
A chip optimized for a specific workload instead of general-purpose execution.
LLM
A large language model that generates text by repeatedly predicting the next token from context.
Token
The text unit used by a model after tokenization; it maps to a vocabulary id.
Attention
A mechanism that lets a token compare its query with keys from other tokens and combine their values.
KV Cache
Cached Key and Value tensors from previous tokens, reused during autoregressive decoding.
FIPS 140-3
A validation standard for the design and operation of cryptographic modules.
CRA
The EU Cyber Resilience Act: lifecycle cybersecurity requirements for products with digital elements placed on the Union market.
CoWoS
An advanced package integrating compute and memory through an interposer.
RSA
A public-key family whose security relies on the difficulty of factoring a large composite integer.
ECC
Public-key cryptography based on the difficulty of elliptic-curve discrete logarithms.
Galois Field
A finite set with well-defined addition, subtraction, multiplication, and division by nonzero elements.
Hardware Root of Trust
A hardware-anchored trusted subsystem that provides difficult-to-bypass foundations for defined security services.
HUK
Device-specific root secret material retained or reconstructed inside a protected boundary and not exported to ordinary software.
Secure Storage
A storage service that combines confidentiality as needed with integrity, ownership isolation, access control, and freshness.
Chain of Trust
A sequence in which an established trusted stage verifies or authorizes the next stage.
Shor
A quantum algorithmic framework that efficiently solves integer factorization and discrete logarithms on a suitable quantum computer.
PQC
Public-key cryptography designed to resist known attacks from both classical and quantum computers.
Wafer-Scale Engine
A processor that keeps a large programmable compute fabric and distributed memory on one silicon wafer.
Dataflow
An execution model in which data arrival and readiness help determine when work can run.
Reticle Stitching
Electrical connections aligned across neighboring lithography fields on an uncut wafer.